1. Field of the Invention
This invention relates to LSI circuit construction of bipolar transistors, and more particularly to a method of fabricating such transistors which results in greatly reduced size.
2. Description of the Prior Art
There are presently two major objectives in current designs of large scale integrated circuits (LSI). First, to provide the maximum number of devices on a chip which is not so large as to be impractical to produce; and second, to maintain a specified operating speed while keeping the power dissipation low. For bipolar LSI, power dissipation is a severe problem. It is common to dissipate one milliwatt per device. For a chip containing 5,000 devices, this results in 5 watts of power dissipation per chip. It is apparent that this problem could become quite severe for chips containing 40 or 50 thousand devices.
Both of the problems given above can be attacked by reducing the size of an individual transistor. This allows more transistors to be placed upon a given sized chip and it reduces the parasitic capacitances of the transistor. The latter result permits operation at a given speed at a higher impedance level, thereby resulting in lower power dissipation.
In conventional LSI circuit construction, bipolar transistors are fabricated by a process which involves several steps of selective impurity diffusion into a semiconductive body or substrate. This process is sometimes called a triple diffusion process because three separate diffusion steps are carried out to form the collector, base, and emitter regions one within the other.
In order to define the regions where the diffusions will occur, a separate masking operation is performed for each of the several diffusions. According to one conventional procedure, the masking operation is performed by a photolithographic process that involves growing a masking oxide layer on the semiconductive substrate, coating the oxide layer with a photoresist, exposing the photoresist to light through a masking pattern, developing the photoresist pattern, and etching the oxide layer through the photoresist pattern until the semiconductive surface is reached and the diffusion regions are thereby defined.
An alternative practical method which has been used to mask selectively against an impurity deposition is as follows. A semiconductor wafer is coated directly with photoresist about one micron or more thick, the photoresist is exposed to light through a masking pattern, and the photoresist pattern is developed. The photoresist pattern remaining on the wafer can act as an in-situ mask against impurity deposition that is performed by an ion accelerator apparatus. The silicon wafer may have a thin surface oxide, in which case the ions are given sufficient energy, such as 130,000 electron volts for 1000 A silicon dioxide layers, to penetrate through the oxide but not through the photoresist. Alternatively, the oxide can be removed before ion implantation, in which case less ion implantation energy is required. After ion implantation, the photoresist is removed and the wafer is placed in a thermal diffusion furnace to diffuse and distribute the ion implanted impurity to the required depth.
The primary factor limiting the reduction of the size of a triple diffused transistor is the registration tolerance of the photolithographic process. The fabrication of a triple diffused bipolar transistor can be thought of in a simplified form as analogous to the fabrication of three nested bath tubs referred to as collector, base, and emitter in descending size. The collector is the largest region and is diffused in the substrate. The base is intermediate in size and is diffused in the collector region. The emitter is the smallest region and is diffused in the base region.
An important design rule for a transistor is that the bottom surfaces of the diffused regions or tubs must not touch one another. This requires that in the vertical dimension, the emitter diffusion layer is shallower than the base diffusion layer and the base diffusion layer is shallower than the collector diffusion layer. In the horizontal dimensions, it requires that the difference in size between adjacent regions or tubs be sufficient to assure that the tolerance with which they are placed within one another does not cause their edges to touch. This tolerance is the factor which limits the reduction of the size of triple diffused transistors.